View NT68P61A_689079.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NT68P61A
8-Bit Microcontroller for Monitor (24K OTP ROM Type)
Features
T T T T T T T T T T T T
40 pin DIP & 42 pin SDIP package Operating Voltage Range: 4.5V to 5.5V CMOS technology for low power consumption Crystal oscillator or ceramic resonator* available 6502 8-bit CMOS CPU core 8MHz operation of frequency 24K bytes of OTP (one time programming) ROM 256 bytes of RAM (which stores EDID for DDC1/2B) One 8-bit pre-loadable base timer 14 channels of 8 bit PWM outputs: 6 channel with 5V open drain and 8 channel with 12V open drain 2 channel A/D converters with 6-bit resolution 24 bi-directional I/O port pins and 1 I/P pin
T T T T T
T T
Hsync/Vsync signal processor Hardware sync signals polarity & freq. evaluator 2 Built-In I C bus interface Supporting VESA DDC1/2B function Six-interrupt sources - INTV (Vsync INT) - INTE (External INT with rising edge trigger) - INTMR (Timer INT ) - INTA (Slave Address Matched INT) - INTD (Shift Register INT) - INTS (SCL GO-LOW INT) Hardware watch-dog timer function Built-In Low Voltage reset circuit (LVRC)
General Description
NT68P61A is a monitor component C for auto-sync and digital controlled applications. It contains a 6502 8-bit CPU core, 256 bytes of RAM used as working RAM and stack area, 24K bytes of OTP ROM**, 14-channel 8bit PWM D/A converters, 2-channel A/D converters for key detection saving I/O pins, one 8 bit pre-loadable base timer, internal Hsync and Vsync signals processor providing mode detection, watch-dog timer preventing 2 system from abnormal operation, and an I C bus interface. The LVRC enables NT68P61A operate properly. Users can store EDID data in the 128 bytes of RAM for DDC1/2B, so that users can save the cost of dedicated EEPROM for EDID. Half frequency output function can save external one-shot circuit. All of these designs create savings in component costs. * The frequency deviation of ceramic resonator has +/- 6% maximum. ** The NT6861 (MASK ROM type) will provide 4/8/12/16/24K bytes program ROM.
1
V1.0
NT68P61A
Pin Configuration
[OE] DAC2 DAC1 DAC0 [VPP] RESET V DD GND OSCO OSCI P15 [CE] P14 [A11] P13/HALFHI [A10] P12/HALFHO [A9] P11/AD1 [A8] P10/AD0 P16/INTE [DB7] P27 [DB6] P26 [DB5] P25 [DB4] P24 [DB3] P23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSYNCI/INTV/ [A14] HSYNCI DAC3 DAC4 DAC5 DAC6 DAC7 [PGM] [MODE0] [MODE1] [MODE2]
[OE] DAC2 DAC1 DAC0 [VPP] RESET V DD NC GND OSCO OSCI P15 [CE] P14 [A11] P13/HALFHI [A10] P12/HALFHO [A9] P11/AD1 [A8] P10/AD0 P16/INTE [DB7] P27 [DB6]P26 [DB5] P25 [DB4] P24 [DB3] P23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36
VSYNCI/INTV HSYNCI DAC3 [PGM] DAC4 [MODE0] DAC5 [MODE1] NC DAC6 [MODE2] DAC7 [A14] P07/HSYNCO [A7] P06/VSYNCO [A6] P05/DAC13 [A5] P04/DAC12 [A4] P03/DAC11 [A3] P02/DAC10 [A2] P01/DAC9 [A1] P00/DAC8 [A0] P31/SCL [A13] P30/SDA [A12] P20 [DB0] P21 [DB1] P22 [DB2]
NT68P61AU
P07/HSYNCO [A7] P06/VSYNCO [A6] P05/DAC13 [A5] P04/DAC12 [A4] P03/DAC11 [A3] P02/DAC10 [A2] P01/DAC9 [A1] P00/DAC8 [A0] P31/SCL [A13] P30/SDA [A12] P20 [DB0] P21 [DB1] P22 [DB2]
35 34 33 32 31 30 29 28 27 26 25 24 23 22
NT68P61A
*[
]: OTP Mode
*[
]: OTP Mode
Block Diagram
V DD GND OSCI OSCO INTE A/D Converter VSYNCI/INTV HSYNCI VSYNCO HSYNCO HALFHI HALFHO H/V Sync Signals Processor Interrupt Controller 8 Bit Base Timer I/O Ports CPU core 6502 SRAM + STACK 256 Bytes PWM DACs Timing Generator OTP Program ROM 24K Bytes IIC BUS
SCL SDA
DAC0 - DAC7 DAC8 - DAC13
AD0 - AD1
P00 - P07 P10 - P15 P16
Watch Dog Timer
LVRC
P20 - P27 P30 - P31
2
NT68P61A
Pin Descriptions
Pin No. 40 Pin 1 42 Pin 1 2 3 4 5 7 8 9 10 11 12 13 14 DAC2 [ OE ] DAC1 DAC0
RESET [ VPP ]
Designation
Reset Init.
I/O
Description
O [I] O O I [P] P P O I I/O I/O [I] P13 P12 P11 I/O [I] I/O [I] I/O [I] P10 I/O [I] P16 I I/O [ I/O ] P30 I/O [I] P31 I/O [I] P00 I/O [I]
Open drain 12V, D/A converter output 2 [OTP ROM program output enable] Open drain 12V, D/A converter output 1 Open drain 12V, D/A converter output 0 Schmitt trigger input pin, low active reset** [OPT ROM program supply voltage] Power Ground Crystal OSC output Crystal OSC input Bi-directional I/O pin Bi- directional I/O pin [OTP ROM program chip enable] Bi- directional I/O pin, shared with half hsync input [OTP ROM program address buffer] Bi- directional I/O pin, shared with half hsync output [OTP ROM program address buffer] Bi- directional I/O pin, shared with A/D converter channel 1 input [OTP ROM program address buffer] Bi- directional I/O pin, shared with A/D converter channel 0 input [OTP ROM program address buffer] Schmitt trigger input pin with internal pull high, shared with external Rising-edge trigger interrupt Bi- directional I/O pin, push-pull structure with high current drive/sink capability [OTP ROM program data buffer] Open drain 5V Bi-direction I/O pin P30, shared with SDA 2 pin of I C bus schmitt trigger buffer [OTP ROM program address buffer] Open drain 5V Bi-direction I/O pin P31, shared with SCL 2 pin of I C bus schmitt trigger buffer [OTP ROM program address buffer] Bi- directional I/O pin, shared with open drain 5V D/A converter output 8 [OTP ROM program address buffer]
2
3 4 5 6 7 8 9 10 11 12 13
VDD GND OSCO OSCI P15 P14 [ CE ] P13/HALFHI [ A11 ] P12/HALFHO [ A10 ] P11/AD1 [ A9 ]
14
15
P10/AD0 [ A8 ]
15 16 - 23
16 17 - 24
P16/INTE P27 - P20 [ DB7 ] [ DB0 ]
24
25
P30/SDA [ A12 ]
25
26
P31/SCL [ A13 ]
26
27
P00/DAC8 [ A0 ]
* [ ]: OTP Mode ** This RESET pin must be pulled high by external pulled-up resistor (5K suggestion), or it will stay low voltage to reset system all the time.
3
NT68P61A
Pin Descriptions (continued)
Pin No. 40 Pin 27 42 Pin 28 P01/DAC9 [ A1 ] 28 29 P02/DAC10 [ A2 ] 29 30 P03/DAC11 [ A3 ] 30 31 P04/DAC12 [ A4 ] 31 32 P05/DAC13 [ A5 ] 32 33 34 35 36 37 38 39 33 34 35 36 38 39 40 41 P06/VSYNCO [ A6 ] P07/HSYNCO [ A7 ] DAC7 [ A14 ] DAC6 [ MODE2 ] DAC5 [ MODE1 ] DAC4 [ MODE0 ] DAC3 [ PGM ] HSYNCI P06 P07 P05 P04 P03 P02 P01 I/O [I] I/O [I] I/O [I] I/O [I] I/O [I] I/O [I] I/O [I] O O [I] O [I] O [I] O [I] I Bi- directional I/O pin, shared with open drain 5V D/A converter output 9 [OTP ROM program address buffer] Bi- directional I/O pin, shared with open drain 5V D/A converter output 10 [OTP ROM program address buffer] Bi- directional I/O pin, shared with open drain 5V D/A converter output 11 [OTP ROM program address buffer] Bi- directional I/O pin, shared with open drain 5V D/A converter output 12 [OTP ROM program address buffer] Bi- directional I/O pin, shared with open drain 5V D/A converter output 13 [OTP ROM program address buffer] Bi- directional I/O pin, shared with vsync out [OTP ROM program address buffer] Bi-directional I/O pin, shared with hsync out [OTP ROM program address buffer] Open drain 12V, D/A converter output [OTP ROM program address buffer] Open drain 12V, D/A converter output [OTP ROM mode select] Open drain 12V, D/A converter output [OTP ROM mode select] Open drain 12V, D/A converter output [OTP ROM mode select] Open drain 12V, D/A converter output [OTP ROM program control] Debouncing & schmitt trigger input pin for video horizontal sync signal, internal pull high, shared with composite sync input Debouncing & schmitt trigger input pin for video vertical sync signal, internal pull high, shared with external interrupt source Bi-directional I/O pin, with internal pulled up 22K resister, only 42 pin SDIP available Bi-directional I/O pin, with internal pulled up 22K resister, only 42 pin SDIP available Designation Reset Init. I/O Description
40
42
VSYNCI/INTV [A14]
VSYNCI
I [I] I/O I/O
-
6 37
NC NC
*[
]: OTP Mode
4
NT68P61A
Functional Descriptions 1. 6502 CPU
The 6502 is an 8-bit CPU that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true indexing capability, programmable stack pointer with variable length stack, a wide selection of addressable memory, and interrupt input options. The CPU clock cycle is 4MHz (8MHz system clock divided by 2). Refer to 6502 data sheet for more details.
7 Accumulator A 7 Index Register Y 7 Index Register X 15 Program Counter PCH PCL 7 7 Stack Pointer SP 7 N V B D I Z 0 C Status Register P 0 0 8 0 0 0
Carry Zero IRQ Disable Decimal Mode BRK Command Overflow Negative
1 = TRUE 1 = Result ZERO 1 = DISABLE 1 = TRUE 1 = BRK 1 = TRUE 1 = NEG
Figure 1. 6502 CPU Registers and Status Flags
5
NT68P61A
2. Instruction Set List
Instruction Code ADC AND ASL BCC BCS BEQ BIT BMI BNE BPL BRK BVC BVS CLC CLD CLI CLV CMP CPX CPY DEC DEX DEY EOR INC INX INY Meaning Add with carry Logical AND Shift left one bit Branch if carry clears Branch if carry sets Branch if equal to zero Bit test Branch if minus Branch if not equal to zero Branch if plus Break Branch if overflow clears Branch if overflow sets Clear carry Clear decimal mode Clear interrupt disable bit Clear overflow Compare accumulator to memory Compare with index register X Compare with index register Y Decrement memory by one Decrement index X by one Decrement index Y by one Logical exclusive-OR Increment memory by one Increment index X by one Increment index Y by one Operation A + M + C A, C A*MA C M7 * * * M0 0 Branch on C = 0 Branch on C = 1 Branch on Z = 1 A * M, M7 N, M6 V Branch on N = 1 Branch on Z = 0 Branch on N = 0 Forced Interrupt PC+2 PC Branch on V = 0 Branch on V = 1 0C 0D 0J 0V A-M X-M Y-M M-1M X-1X Y - 1 Y A M A M+1M X+1X Y+1Y
6
NT68P61A
Instruction Set List (continued)
Instruction Code JMP JSR LDA LDX LDY LSR NOP ORA PHA PHP PLA PLP ROL ROR RTI RTS SBC SEC SED SEI STA STX STY TAX TAY TSX TXA TXS TYA Meaning Jump to new location Jump to subroutine Load accumulator with memory Load Index register X with memory Load Index register Y with memory Shift right one bit No operation Logical OR Push accumulator on stack Push status register on stack Pull accumulator from stack Pull status register from stack Rotate left through carry Rotate right through carry Return from interrupt Return from subroutine Subtract with borrow Set carry Set decimal mode Set interrupt disable status Store accumulator in memory Store index register X in memory Store index register Y in memory Transfer accumulator to index X Transfer accumulator to index Y Transfer stack pointer to index X Transfer index X to accumulator Transfer index X to stack Pointer Transfer index Y to accumulator Operation (PC+1) PCL, (PC+2) PCH PC + 2 , (P+1) PCL, (PC+2) PCH MA MX MY 0 M7 * * * M0 C No operation (2 cycles) A + M A A P A P C M7 * * * M0 C C M7 * * * M0 C P , PC PC , PC+1 PC A - M - C A, C 1C 1 D 1J A M X M Y M A X AY SX XA X S YA
* Refer to 6502 programming data book for more details.
7
NT68P61A
3. OTP ROM: 24K X 8 bits
The OTP ROM storing application program code, executed by 6502 CPU, has a capacity of 24K X 8 bits, addressed from $A000 to $FFFF. It is programmed by the universal EPROM writer through a conversion adapter. In PROGRAMMING mode, OTP ROM is integrated with system and cannot be directly accessed. When using the OTP ROM alone, first enter the PROGRAMMING mode by setting: RESET = VPP. At this time, through multiplex pins, normal procedures are used to program and verify the OTP ROM block with the universal programmer. OTP ROM Mega Cell D.C. Electrical Characteristics (READ Mode) (VDD = 5V , TA = 25C, unless otherwise specified) Symbol VIH VIL IIL IOH Output Voltage IOL IDD ISTB1 Operating Current Standby Current 1 1 100 Input Voltage Input Current -400 Parameter Min. VDD-0.3 -0.3 Typ. Max. VDD+0.3 0.3 +/-10 Unit V V A A A A A VDD =5V, VOH = 4.5V VDD =5V, VOL = 0.5V f = 4MHz 2 3 Test Conditions Note 1 1
Notes: 1. All inputs and outputs are CMOS compatible 2. f = 4MHz, Iout = 0mA, CE = VIH, VDD = 5V 3. CE = VIH, OE = VIL, VDD = 5V OTP ROM Mega Cell l A.C. Electrical Characteristics (READ Mode) (VDD = 5V, TA = 25C, unless otherwise specified) Symbol Tcyc T12 Tacc Tce Tst Toh Parameter Cycle Time Nonoverlap Time to PH1 & PH2 Address Access Time OTPCE to Output Valid Output Data Setup Time Output Data Hold Time 20 0 Min. 250 5 65 145 145 Max. Unit ns ns ns ns ns ns 4.5V < VDD < 5.5V Conditions
OTP ROM MEGA CELL A.C. Test Conditions Output Load Input Pulse Rise and Fall Times Input Pulse Levels Timing Measurement Reference Level 1 CMOS Gate and CL = 10pF 10ns Max. 0V to 5V Inputs 0V and 5V outputs 0.3V and 4.7V
8
NT68P61A
OTP ROM Mega Cell Timing Waveforms (READ Mode)
T12 Tcyc
PH1 PH2
A0 - A14
OTPCE
DB0 - DB7 Tacc & Tce Tst Toh
OTP ROM Mega Cell A.C. Electrical Characteristics (PROGRAMMING Mode) (TA = 25C, unless otherwise specified) Symbol VDD VPP VIH VIL IIL IOH IOL IDD IPP Programming Current Input Current Output Current -400 1 30 20 Input Voltage Parameter Supply Voltage 10.5 2 -0.3 Min. Typ. 6 Max. 6.5 12.75 VDD +0.3 0.8 +/-10 Unit V V V V A A mA mA mA VPP = 12.75V VDD = 5V, VOH = 4.5V VDD = 5V, VOL = 0.5V Test Conditions Note 4
Note: 4. For reliability concern, we suggested VDD = 6V & VPP = 12.75V for test OTP ROM AC characteristics in PROGRAMMING mode, using the same condition for the universal programmer supply voltage.
9
NT68P61A
OTP ROM Mega Cell D.C. Electrical Characteristics (PROGRAMMING Mode) (TA = 25C, unless otherwise specified) Symbol Tms Tmh Tas Tah Tces Tceh Tds Tdh Tvs Tpw Tdv Tdf Parameter Mode Decode Setup Time Mode Decode Hold Time Address Setup Time Address Hold Time CE Setup Time CE Hold Time Data Setup Time Data Hold Time VPP Setup Time Program Pulse Width
OE to Output Valid OE to Output in High-Z
Min. 2 2 2 2 2 2 2 2 2
Typ.
Max.
Unit ms ms ms ms ms ms ms ms ms
Test Conditions
Note
100 150 90
ms ns ns CE = VIL
OTP ROM Mega Cell A.C. Test Conditions Output Load Input Pulse Rise and Fall Times Input Pulse Levels Timing Measurement Reference Level 1 TTL Gate and CL = 100pF 10ns Max. 0.45V to 2.4V Inputs 0.8V and 2.2V Outputs 0.8V and 2.4V
Note: 5. VDD must be applied simultaneously or before VPP and cut off simultaneously or after VPP. 6. Removing the device from power or setting the device with VPP = 12.75V may cause permanent damage to the device.
10
NT68P61A
OTP ROM Mega Cell Timing Waveforms (PROGRAM Mode)
Tms Tmh MODE DEC. TEST = VPP, MODE [0..2] = 000; Tvs VPP Tas A0 - A14 Tah
CE Tceh
Tces OE
Tdf DOUT Tdv PGM
DB0 - DB7
D IN
Tds
Tpw
Tdh
11
NT68P61A
OTP ROM Mega cell Mode Selection
RESET = 12.75V, OSCI = VIL, P16 = VIH, DAC0 = VIL
Mode [0..2]
Mode
CE
OE
VPP
DB0 DB7 high-Z data in data out high-Z data in "0" data in data in
not VPP VPP VPP VPP VPP VPP VPP VPP VPP VPP
--000 000 000 000 001 010 011 100 101
Normal Operating Output Disable Program Program Verify Program Inhibit (Standby) Security (Program) Word-line Stress Bit-line Stress OTP Row (after pkg) OTP Column (after pkg)
VIH VIH VIL VIH VIH VIH
VIH VIH VIL VIH VIH
VPP VPP VPP VPP VPP VPP VPP VPP
* The security byte is at address $0000. READ PROGRAM NT68P61A's OTP ROM mega cell has 2 control pins. CE (Chip Enable) controls the operation power and is used for device selection. The OE (Output Enable) controls the output buffers. OUTPUT DISABLE If OE = VIH, the outputs will be in a high impedance state. Two or more ROMs can be connected together on a common bus. STANDBY By applying a low power level to the CE input, the chip enters STANDBY reducing the operating current to 100A. Initially, all bits are in "1" state which is the erased state. The program operation is to introduce "0" data into the desired bit locations by electrical programming. When the VPP input is at 12.75V and CE is at VIH, the chip enters the PROGRAMMING mode. PROGRAM VERIFY The VERIFY mode is to check if the desired data is correctly programmed on the programmed bit. The VERIFY is accomplished with CE at VIH, VPP input is at 12.75V, and OE = VIL. PROGRAM INHIBIT Using this mode, programming of two or more OTP ROMs in parallel with different data is accomplished. All inputs except for CE and OE may be commonly connected, and a TTL high level program pulse is applied to the CE of the desired device only and TTL high level signal is applied to the other devices.
12
NT68P61A
4. RAM: 256 X 8 bits
256 X 8-bit SRAM is used for data memory and stack. The RAM addressing range is from $0080 to $017F. From $0100 to $017F is used as the EDID data buffer when activating DDC1/2B mode transmission. The contents of RAM are undetermined at power-up and are not affected by system reset. Software programmers can allocate stack area in the RAM by setting stack pointer register S. Because the 6502 default stack pointer is $01FF, programmers must set register S to FFH when starting the program, so the stack area will map $01FF - $0180 to $00FF - $0080. as; LDX TXS #$FF
$0000 $0025 $0080 RAM $00FF $0100 EDID $017F $0180 System Registers Unused
stack pointer
Unused
$BFFF $A000 (24K Bytes)
OTP ROM
$FFFC $FFFD $FFFE $FFFF
RST-L RST-H IRQ-L IRQ-H RESET vector IRQ vector
13
NT68P61A
5. System Registers
Addr. $0000 $0001 $0002 $0003 $0004 $0005 Register PT0 PT1 PT2DIR PT2 PT3 MD CON INIT FFH 7FH FFH FFH 03H 07H Bit7 P07 Bit6 P06 P16 Bit5 P05 P15 Bit4 P04 P14 Bit3 P03 P13 Bit2 P02 P12 Bit1 P01 P11 Bit0 P00 P10 RW RW W RW RW R W R W R R R R W W R W R W
P27OE
P27 HCNTOV
P26OE
P26 VCNTOV
P25OE
P25 HSYNCI
P24OE
P24 VSYNCI
P23OE
P23 INSEN HPOLI
P22OE
P22 HSEL VPOLI
P21OE
P21 P31 S/ C S/ C
P20OE
P20 P30 MD1/ 2 MD1/ 2
$0006
HV CON
2FH
HPOLO $0007 $0008 $0009 $000A $000B $000C $000D HCNT L HCNT H VCNT L VCNT H SYNCON ENDAC AD0 REG 00H 00H 00H 00H FFH FFH C0H HCL7 VCL7 NOHALF ENAD1 CEND CSTA $000E $000F AD1 REG IEX 00H 00H AD15 IEINTS AD14 IEINTD AD13 IEINTA AD12 IEINTR AD11 IEINTE HCL6 VCL6 ENHALF ENAD0 HCL5 VCL5 ENDK13 AD05 HCL4 VCL4 FRUN ENDK12 AD04 HCL3 HCH3 VCL3 VCH3 FRFREQ ENDK11 AD03 HCL2 HCH2 VCL2 VCH2 HALFPOL ENDK10 AD02 HCL1 HCH1 VCL1 VCH1 ENH ENDK9 AD01
VPOLO HCL0 HCH0 VCL0 VCH0 ENV ENDK8 AD00
AD10 IEINTV
14
NT68P61A
System Registers (continued)
Addr. $0010 $0011 $0012 $0013 $0014 $0015 Register IRQX CLR FLG CLR WDT II ADR II DAT II STS INIT 00H 00H FFH 00H 08H Bit7 CLRHOV 0 AR7 SR7 Bit6 CLRVOV 1 AR6 SR6 Bit5 IRQINTS CLRINTS 0 AR5 SR5 START START BT5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 Bit4 IRQINTD CLRINTD 1 AR4 SR4 STOP STOP BT4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 Bit3 IRQINTA CLRINTA 0 AR3 SR3 Bit2 IRQINTR CLRINTR 1 AR2 SR2 Bit1 IRQINTE CLRINTE 0 AR1 SR1 RXAK ENDDC BT3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 TRX BT2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 BT1 TBS DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 BT0 ENBT DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 Bit0 IRQINTV CLRINTV 1 SR0 R W W W RW R W W W RW RW RW RW RW RW RW RW RW RW RW RW RW RW
$0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0020 $0021 $0022 $0023 $0024 $0025
BT BT CON DACH0 DACH1 DACH2 DACH3 DACH4 DACH5 DACH6 DACH7 DACH8 DACH9 DACH10 DACH11 DACH12 DACH13
00H 03H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H
BT7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7
BT6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6
Note: The line above a writable signal name indicate an active low signal The dash line in these control register indicate an undefined bit The address of control register from $0026 to $007F are not used.
15
NT68P61A
6. Timing Generator
This block generates the system timing and control signal to be supplied to the CPU and on-chip peripherals. A crystal quartz, ceramic resonator, or an external clock signal provided to the OSCI pin generates 8MHz system clock, (4 MHz for CPU), Although internal circuits have a feedback resistor and capacitor included, components may be externally added to ensure proper operation. The typical clock frequency is 8MHz. This frequency will affect the operation of on-chip peripherals whose operating frequency is based on the system clock .
OSCI 8MHz OSCO (1) NT68P61A
External Clock
OSCI
Unconnected
OSCO (2) NT68P61A
Figure 2. Oscillator Connections
7. A/D Converter
The analog to digital converter is a single 6-bit successive approximation converter. Analog voltage is supplied from external sources to the A/D input pins and the results of the conversion are stored in the 6-bit data latch registers ($000D & $000E). The A/D converter is controlled by the control bits in the A/D control register ENDAC. Refer to the A/D channel format table A/D input pins activation. A conversion is started by setting a '0' to the CONVERSION START bit ( CSTA ) in the A/D control register ($000D). This automatically sets the CONVERSION END bit ( CEND ) to '1'. When a conversion has been finished, CEND bit automatically clears to '0'. The A/D conversion data in the AD LATCH registers ($000D & $000E) is valid digital data. The analog voltage to be measured should be stable during the conversion operation. The variation should exceed 1/2 LSB for accuracy in measurement. Please refer Figure 3 for checking the linearity of A/D. A/D Channel Format Table
ENAD1 ENAD0
P11 line AD1 AD1 P11 P11
P10 line AD0 P10 AD0 P10
0 0 1 1
0 1 0 1
16
NT68P61A
A/D Channel Control Register
Addr. $000C $000D Register ENDAC AD0 REG INIT FFH C0H Bit7 ENAD1 CEND CSTA $000E AD1 REG 00H AD15 AD14 AD13 AD12 AD11 AD10 Bit6 ENAD0 Bit5 ENDK13 AD05 Bit4 ENDK12 AD04 Bit3 ENDK11 AD03 Bit2 ENDK10 AD02 Bit1 ENDK9 AD01 Bit0 ENDK8 AD00 W R W R
Input Voltage 0.12 0.37 0.53 0.78 1 1.28 1.54
Digital Value 0 ($00) 1 ($01) 7 ($07) 10 ($0A) 14 ($0E) 17 ($11) 20 ($14)
Input Voltage 1.79 2.03 2.27 2.51 2.76 3 3.25
Digital Value 23 ($17) 27 ($1B) 30 ($1E) 33 ($21) 36 ($24) 40 ($28) 43 ($2B)
Input Voltage 3.5 3.75 3.99 4.22 4.46 4.7 4.95
Digital Value 46 ($2E) 49 ($31) 52 ($34) 56 ($38) 63 ($3F) 63 ($3F) 63 ($3F)
70 These digitals have 1 LSB deviation 60 Linear Range Digital Value 50
40
30
20 10 VDD 0 0.2 0.3 0.4 0.6 0.7 0.8 1
0
Input Voltage
Figure 3. A/D Converter Linearity Diagram
17
NT68P61A
8. PWM DACs (Pulse Width Modulation D/A Converters)
There are 14 PWM D/A converters with 8-bit resolution in NT68P61A. Eight of these D/A (DAC0 - DAC7) converters are open-drain output structures with 12V applied (maximum), and the other six D/A converters (DAC8 - DAC13) are open-drain output structures with 5V applied (maximum). The PWM frequency is 31.25 KHz on 8 MHz system clock. Use of a different oscillator frequency will result in different PWM frequency. As DAC8 - DAC13 are shared with I/O port pins, user can write '0' to corresponding enable bit in the ENDAC control register to activate each of DACH8 - 13. There are 14channel readable DACH registers corresponding to 14 D/A converters. Each PWM output pulse width is programmable by setting the 8 bit digital to the corresponding DACH registers. When these DACH registers are set to 00H, the DAC will output LOW (GND level) and each bit addition will add 125ns pulse width. After reset, all DAC outputs are set to 80H (1/2 duty output). Refer to Figure 4 for the detailed timing diagram of PWM D/A output.
8MHz Fosc PWM value: 00 255 0 1 2 m m+1 m+2 255 0 1
01
02
m
255 (FF)
Figure 4. The DAC Output Timing Diagram and Wave Table
DKVL7 0 0 0 0 0 1 1
DKVL6 0 0 0 0 0 1 1
DKVL5 0 0 0 0 0 1 1
DKVL4 0 0 0 0 0 1 1
DKVL3 0 0 0 0 0 1 1
DKVL2 0 0 0 0 1 1 1
DKVL1 0 0 1 1 0 1 1
DKVL0 0 1 0 1 0 0 1
DAC Output Duty Cycle GND 1/256 Vref. 2/256 Vref. 3/256 Vref. 4/256 Vref. X /256 Vref. 254/256 Vref. 255/256 Vref.
The DAC value correspondent to PWM output
* Vref. is 12V or 5V
18
NT68P61A
Addr. $000C $0018 $0019 $001A $001B $001C $001D $001E $001F $0020 $0021 $0022 $0023 $0024 $0025
Register ENDAC DACH0 DACH1 DACH2 DACH3 DACH4 DACH5 DACH6 DACH7 DACH8 DACH9 DACH10 DACH11 DACH12 DACH13
INIT FFH 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H 80H
Bit7 ENAD1 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7 DKVL7
Bit6 ENAD0 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6 DKVL6
Bit5 ENDK13 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5 DKVL5
Bit4 ENDK12 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4 DKVL4
Bit3 ENDK11 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3 DKVL3
Bit2 ENDK10 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2 DKVL2
Bit1 ENDK9 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1 DKVL1
Bit0 ENDK8 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 DKVL0 W RW RW RW RW RW RW RW RW RW RW RW RW RW RW
DAC control register ($000C) and DAC value register ($0018 - $0025) Control Bit Description:
Addr. $000C $0018 Register ENDAC DACH0 INIT FFH 80H Bit7 ENAD1 DKVL7 Bit6 ENAD0 DKVL6 Bit5 ENDK13 DKVL5 Bit4 ENDK12 DKVL4 Bit3 ENDK11 DKVL3 Bit2 ENDK10 DKVL2 Bit1 ENDK9 DKVL1 Bit0 ENDK8 DKVL0 W RW
ENDK8 : Enable DAC channel 8; When clearing this bit to '0', the I/O port, P00, will change to DAC channel 8. When setting this bit to '1', the I/O port will restore to P00. ENDK9 - ENDK13 : The manipulation is the same as ENDK8 bit, and control DAC channel 9 - 13. DACH0 (DKVL0 - DKVL7): Setting DAC output waveform of DAC channel 8. Please check Figure 3 for the timing diagram and wave table. DACH1 - DACH13: The manipulation is the same as DACH0 register, and control DAC channel 1 - 13.
19
NT68P61A
9. RESET
NT68P61A can be reset by the external reset pin or by the internal watch-dog timer. This resets or starts the microcontroller from a power-down condition. During the time that this reset pin is held low (*reset line must be held low for at least two CPU clock cycles), writing to or from the C is inhibited. When positive edge is detected on the reset input, the C will immediately begin reset sequence. After a system initialization time of six CPU clock cycles, the mask interrupt flag will be set and the C will load the program counter from the memory vector locations $FFFC and $FFFD. This is the start location for program control. To improve noise immunity a Schmitt Trigger buffer is provided at the RESET . Reset status is as follows: 1. PORT0 PORT1. PORT2. PORT3 pins will act as I/O ports with HIGH output. 2. Sync processor counters reset and VCNT | HCNT latches cleared 3. All sync outputs are disabled 4. Base timer is disabled and cleared 5. A/D converter is disabled and stopped 6. DDC1/2B function is disabled 7. PWM DAC0 - DAC7 output 50% duty waveform and DAC8 - DAC13 is disabled 8. Watch-dog timer is cleared and enabled This RESET pin must be pulled high by external pulledup resistor (5K suggestion), or it will stay low voltage to reset system all the time.
10. Watch-dog timer (WDT) and Low Voltage Reset Circuit (LVRC)
NT68P61A implements a watch-dog timer reset to avoid system shut-down or malfunction. The clock of the WDT is from on-chip RC oscillator not requiring any external components. The WDT runs regardless if the clock of the OSCI/OSCO pins of the device has been stopped. The WDT time interval is about 0.5 second. The WDT must be cleared within every 0.5 second when software is in normal sequence, otherwise the WDT will overflow and cause reset. The WDT is cleared and enabled after system is reset. It cannot be disabled by software. Users can clear the WDT by writing 55H to CLRWDT register. NT68P61A will check voltage level of power supply. When the voltage level of power supply is below a threshold of 4.0V, the LVRC will issue a reset output to the chip. After the power supply is restored to 4.0V and above, the LVRC will keep reset signal low for 10mS and then restore to high voltage. A power glitch of pulse width less than 1s will be ignored and no reset will occur. This allows the C enter the reset state in a good condition. Refer to Figure 5 for the timing diagram.
as;
LDA STA Addr.
#$55 $0012 Register CLR WDT INIT Bit7 0 Bit6 1 Bit5 0 Bit4 1 Bit3 0 Bit2 1 Bit1 0 Bit0 1 W
$0012
Vcc = 5.0 V
4.0 V
GND
System Reset
Hold 10 mS
Figure 5. LVR Reset Timing Diagram
20
NT68P61A
11. Interrupt Controller
The C will complete the current instruction being executed before recognizing the interrupt request. At this time, the interrupt mask bit in the status register will be examined. If the interrupt mask bit is not set, C will begin interrupt sequence. The program counter and processor status register are stored in the stack. C will then set the interrupt mask flag HIGH so that no further interrupts occur. At the end of this cycle, the program counter will be loaded from addresses $FFFE & $FFFF, transferring program control to the memory vector located at these addresses. Six interrupt sources are available in this system: - INTV INT (Vsync INT): Rising edge of every Vsync pulse - INTE INT (External INT): Rising edge of external interrupt pulse - INTMR INT (Timer INT): As the Base Timer counter overflow and counting from $FF to $00 - INTA INT (Address Matched INT): External device calling NT68P61A in DDC2 mode communication - INTD INT (Shift Register INT): Shift register is empty or receiving a new byte data in DDC1 & DDC2 mode communication - INTS INT (SCL Go-Low INT): External device proceed a DDC2 communication external pins (INTV & INTE), base timer overflow (INTR), SCL line go-low (INTS), and serial bus interrupt (INTA & 2 INTD). The serial bus interrupt is generated by the I C 2 circuit as described in under I C bus interface sections. The interrupt enable (IEX) bit will effects the interrupt process if the IRQX has already been set. Once IEX bit is set, its corresponding interrupt will generate an interrupt source for 6502 CPU. The IRQX will be set no matter the IEX bit enable or not. The interrupt request is generated when IRQX and IEX are both '1'. The IRQX remains in HIGH state unless the CLRIRQ register is cleared (write '1' to correspondent bit in CLRIRQ register). The interrupt enable register (IEX) and interrupt request register (IRQX) are memory mapped registers which can only be accessed or tested by program. These registers are cleared to '0' at initialization after the chip is reset . When interrupt occurs, CPU jumps to $FFFE & $FFFF to execute interrupt service routine and finds which one of the interrupt sources is active by checking the IRQX. Upon entering the interrupt service routine, the IRQX that caused the interrupt service must be cleared in the interrupt service routine program. CPU clears IRQX by writing '1' to the corresponding bit in CLRIRQ register. If more than one interrupt is pending and waiting to be served, each is executed by priority. Priority is defined by the programmer.
Three memory mapped registers are used to control the interrupt operation. The IRQX is set by the rising edge of Control bit description:
ADDR. $000F $0010 $0011 REGISTER IEX IRQX CLR FLG INIT 00H 00H 00H Bit7 CLRHOV Bit6 CLRVOV Bit5 IEINTS IRQINTS CLRINTS Bit4 IEINTD IRQINTD CLRINTD Bit3 IEINTA IRQINTA CLRINTA Bit2 IEINTR IRQINTR CLRINTR Bit1 IEINTE IRQINTE CLRINTE Bit0 IEINTV IRQINTV CLRINTV W R W
IRQINTS is the interrupt flag for SCL- At DDC2B TRANSMISSION mode, it is set when SCL line changes from '1' to '0'. IEINTS enable 6502 interrupt for INTS. - When this bit is set to '1' and IRQINTS flag is set, 6502 will accept interrupt source and jump to interrupt service routine assigned by interrupt vector. CLRINTS clears INTS interrupt flag. - Before returning from interrupt service routine, this flag must be cleared. The manipulation of other interrupt source is the same as INTS. CLRHOV & CLRVOV: Clear the overflow flag of H/V counter and reset H/V counter to zero.
21
NT68P61A
12. I/O PORTs
NT68P61A has 25 pins dedicated to input and output. These pins are grouped into 4 ports . 12.1. Port0: P00 - P07 Port0 is an 8-bit bi-directional CMOS I/O port with PMOS as internal pull-up (Figure 6). Each pin of Port0 may be bit programmed as an input or output port without the software controlling the data direction register. When Port0 works as output, the data to be output is latched to the port data register and output to the pin. Port0 pins that have '1's written to them are pulled high by the internal PMOS pull-ups. In this state they can be used as input, then the input signal can be read. This port outputs high after reset .
Addr. $0000 Register PT0 INIT FFH Bit7 P07 Bit6 P06 Bit5 P05
P00 - P05 are shared with DAC8 - DAC13 respectively. If user sets ENDK8 - ENDK13 LOW in ENDAC register, P00 - P05 will act as DAC8 - DAC13 respectively (Figure 7). After the chip is reset, ENDK - ENDK13 will enter HIGH state and P00 - P05s will act as I/O ports. P06, P07 are shared with VSYNCO & HSYNCO respectively. If user sets ENH , ENV to low in SYNCON register, P06, P07 will act as VSYNCO & HSYNCO respectively (Figure 8). After the chip is reset, ENH , ENV , will enter high state and P06, BP07 will act as I/O pins.
Bit4 P04
Bit3 P03
Bit2 P02
Bit1 P01
Bit0 P00 R W W W
$000B $000C
SYNCON ENDAC
FFH FFH
NOHALF ENAD1
ENHALF ENAD0
ENDK13
FRUN ENDK12
FRFREQ ENDK11
HALFPOL ENDK10
ENH ENDK9
ENV ENDK8
PWM
Vcc
PWM Data In
Output
I/O
Figure 7. PWM Output Structure
Vcc
Data Out
Data In
O/P
Data Out
Figure 6. I/O Structure
22
NT68P61A
Figure 8. Output Structure
23
NT68P61A
12.2. Port1: P10 - P16 Port10-Port15 are 6-bit bi-directional CMOS I/O ports with PMOS as the internal pull-up (Figure 6). Port16 is an input pin only. Each bi-directional I/O pin may be bit programmed as an input or output port without software controlling the data direction register. When Port1 works as output, the data to be output is latched to the port data register and output to the pin. Port1 pins that have '1's written to them are pulled high after reset. P10, P11 are shared with AD0 & AD1 input pins respectively. If user clears the ENADX bit in the ENDAC control register to low, A/D converters will activate simultaneously. After the chip is reset, ENADX bits enter HIGH state and P10, P11 act as I/O pins.
Addr. $0001 $000C $000D Register PT1 ENDAC AD0 REG INIT 7FH FFH C0H Bit7 ENAD1 CEND CSTA $000E $000F AD1 REG IEX 00H 00H AD15 IEINTS AD14 IEINTD AD13 IEINTA AD12 IEINTR AD11 IEINTE AD10 IEINTV Bit6 P16 ENAD0 Bit5 P15 ENDK13 AD05
P12, P13 are shared with half signals input and output pins by accessing SYNCON control register. If user clears the ENHALF bit to low, P13 will switch to HALFHI pin (input pin) and P12 will switch to HALFHO pin (output pin, Figure 8). Refer to half frequency function in the H/V sync processor paragraph concerning HALFHI & HALFHO pin. After the chip is reset, the ENHALF bits will enter HIGH state and P12, P13 will act as I/O pins. P16 has a Schmitt Trigger input buffer (Figure 9) and is shared with the external interrupt pin if set the IEINTE bit in IEX control register. Refer to 'Interrupt Controller' section above for function details.
Bit4 P14 ENDK12 AD04
Bit3 P13 ENDK11 AD03
Bit2 P12 ENDK10 AD02
Bit1 P11 ENDK9 AD01
Bit0 P10 ENDK8 AD00 RW W R W R W
Vcc
Vcc
Data Out
.
I/P Data Input
I/O
Data OE
Figure 9. Schmitt Input Structure
Data In
Figure 10. I/O Structure
24
NT68P61A
12.3. Port2: P20 - P27 Port2, an 8-bit bi-directional I/O port (Figure 10), which may be programmed as an input or output pin by the software control. When setting the PT2DIR control bit to '0', its corresponding pin will act as output pin. Clearing PT2DIR bit to '1', acts as an input pin. When programmed as an input, it has an internal pull-up resistor. When programmed as an output, the data to be output is latched to the port data register and output to the pin with push-pull structure. If programmed as an output pin, user can read out its correspondent control bit about what user has written before. If programmed as an input pin, user can read out what the I/O pin status outside. This port acts as an input port after reset. Addr. $0002 $0003 Register PT2DIR PT2 INIT FFH FFH Bit7
P27OE
Bit6
P26OE
Bit5
P25OE
Bit4
P24OE
Bit3
P23OE
Bit2
P22OE
Bit1
P21OE
Bit0
P20OE
W RW
P27
P26
P25
P24
P23
P22
P21
P20
12.4. Port3: P30 - P31 Port3 is an 2 bit bi-directional open-drain I/O port (Figure 11). Each pin of Port3 may be bit programmed as an input or output pin with open drain structure. When Port3 works as an output, the data to be output is latched to the port data register and output to the pin. For Port3 pins that have '1's written to them, user must connect PORT3 with external pulledup resistor and then PORT3 can be used as input (the input signal can be read). This port outputs high after reset . 2 P30, BP3 include Schmitt Trigger buffer for noise immunity and can be configured as the I C pins SDA & SCL respectively. If set ENDDC to LOW in IISTS control register, P30, P31 will act as SDA, SCL respectively. After the chip is reset, ENDDC will be in HIGH and PORT3 will act as I/O pins. Addr. $0004 $0015 Register PT3 II STS INIT 03H 0FH Bit7 Bit6 Bit5 START START Bit4 STOP STOP Bit3 ENDDC
Bit2 TRX
Bit1 P31 RXAK
Bit0 P30 RW R W
I/O
Data Out
Data In
Figure 11. Open Drain I/O Structure
25
NT68P61A
13. H/V Sync Signals Processor
The functions of the sync processor include polarity detection, Hsync & Vsync signals counting, programmable sync signals output, free running signal generator and composite sync separation. The processor properly handles either composite or separate sync signal inputs as well as no sync signal input. The input at HSYNCI can be either a pure horizontal sync signal or a composite sync signal. For the sync waveform refer to Figures 12 and 13. The sync processor block diagram is shown in Figure 17. Both VSYNCI & HSYNCI pins have a Schmitt Trigger and filtering process to improve noise immunity. Any pulse that is shorter than 125ns will be regarded as a glitch and will be ignored. 13.1. V & H Counter Register: VCNTL/H, HCNTL/H Vsync counter: VCNTL/H, the 12-bit read only register, contains information of the Vsync frequency. An internal counter counts the numbers of 8s pulse between two Vsync pulses. When the next Vsync signal is recognized, the counter is stopped and the VCNT register latches the counter value. The counted data can be converted to the time duration between two successive Vsync pulses by 8s. If no Vsync comes, the counter will overflow and set VCNTOV bit (in HVCON register) to HIGH (see Figure 14). Once the VCNTOV sets to HIGH, it keeps in HIGH state unless cleared by CLRVOV bit (in CLRFLG register) to HIGH. When user clears the CLRVOV bit, the VCNT counter will be reset to zero and begin to count again. Hsync counter: HCNTL/H, the other 12-bit read only register pairs contain the numbers of Hsync pulse between two Vsync pulses (see Figure 15), and the data can be read to determine if the frequency is valid and to determine the VIDEO mode. If the HSEL bit sets to HIGH, the internal counter counts the Hsync pulses between two Vsync pulses. If the HSEL bit clears to LOW, the internal counter will be reset and begin counting the Hsync pulses in each 8.192ms interval (see Figure 16). The counted value will be latched by the HCNTL/H register pairs which are updated by every Vsync pulse or 8.192ms interval. If the counter overflows, the HCNTOV bit (in HVCON register) will be set to HIGH. Once the HCNTOV sets to HIGH, it remains in the overflow HIGH state unless cleared by CLRHOV (in CLRFLG register) to HIGH. When user clears the CLRHOV bit, the HCNT counter will be reset to zero.
(a) Positive polarity
(b) Negative polarity
Figure 12. Separate H Sync. Waveform
(a) Positive Polarity
(b) Negative Polarity
Figure 13. Composite H Sync. Waveform
26
NT68P61A
Latch VCNT register Reset V sync. counter Start pulse counting
a a a
Latch VCNT register Reset V sync. counter Start pulse counting
VSYNCI
8 s
Figure 14. Vsync Counter Operation
Latch HCNT register Reset H sync. counter Start pulse counting
a a a
VSYNCI
Figure 15. Hsync Counter Operation Using Vsync Pulse
Latch HCNT register Reset H sync. counter Start pulse counting
a a a
HSEL = Low 8.192 ms
Figure 16. Hsync Counter Operation Using 8.192ms Time Interval
27
a
a
a
HSYNCI
a
a
a
HSYNCI
a
a
a
Sampling Clock
Latch HCNT register Reset H sync. counter Start pulse counting
Latch HCNT register Reset H sync. counter Start pulse counting
NT68P61A
VCNTL VCNTH Control Logic V sync. Latch Enable
S/C
VSYNC INPUT Schmitt Trigger Digital Filter 1 0 8.192 ms 0 1
8 s
Enable V sync. counter Reset
V
HSEL
Enable H sync. counter Reset
HSYNC INPUT
Schmitt Trigger
Digital Filter
Sync Separator
H
H&V Sync. Polarity Detector
H sync. Latch HPOLO
Enable
HCNTL HCNTH
HPOLI
H
H Sync. Output Control
HSYNCO
FREE_RUN Control
S/C V
0 1 VPOLI
V
V Sync. Output Control
VSYNCO
VPOLO
Figure 17. Sync. Processor Block Diagram
28
NT68P61A
13.2. Sync Processor Control Register: Composite sync: User has to determine whether the incoming signal is separate sync or composite sync and set S/ C & HSEL bit properly. If composite sync signal is input, after set S/ C to '0', the sync separator block will be activated ( please refer figure 18). During Vsync pulse the Hsync will be inserted Hsync pulse by hardware circuit and the pulse width of inserted pulse is 2s fixed. According to the last Hsync pulse outside the Vsync pulse duration, the hardware will arrange the interval of these hardware interpolated pulse. So the insertion of these Hsync pulse will be continued inside the Vsync pulse duration no matter what the Hsync pulse originally exist or not. These inserted Hsync pulse have 0.5s phase deviation maximum. The Vsync pulse can be extracted by hardware from composite signal, and the output of Vsync signal delay time will be limited bellow 20ns. For inserting Hsync pulse safely, the extracted Vsync pulse will be widen about 9s. Because evenly putting the Hsync pulse, the last inserted Hsync pulse will have different frequency from original ones. System will not implement this insertion function, user must clear INSEN bit in the MD_CON control register to activate this function. After reset, the HSEL , S/ C & INSEN bits default value is HIGH and clear the VCNT | HCNT counter latches to zero. Polarity: The detection of Hsync or Vsync polarity is achieved by hardware circuits sample the sync signal's voltage level periodically. The user can read HPOLI & VPOLI bit in HVCON register, from which bit = '1' representing positive polarity and '0', negative polarity. The user can read HSYNCI and VSYNCI bit in HVCON register to detect H & V sync input signal. The user can control the polarity of H & V sync output signal by writing the appropriate data to the HPOLO and VPOLO bits in the HVCON register, '1' represents positive polarity and '0', negative polarity. Sync output: In pin assignment, VSYNCO & HSYNCO represent Vsync & Hsync output which are shared with P06 & P07 respectively. If set ENV & ENH to '0' in SYNCON register, P06 & P07 will act as VSYNCO & HSYNCO pin. When input sync is separate signal, the V/HSYNCO will output the same signal as input sync signal without delay. But if input sync is composite signal, the VSYNCO signal will have a delay time of about 4s to 8s. The HSYNCO has no delay output and still has Vsync pulse among Hsync pulse (i.e. the signal on HSYNCI pin directly output to HSYNCO pin.) Free run signal output: The user can set FRUN to '0' bit in SYNCON register, then VSYNCO will output 61Hz Vsync signal and HSYNCO will output 62.5KHz Hsync signal default (Refer to Figure 20). When FRFREQ bit clears to '0', the HSYNCO pin will output 41.7 KHz Hsync signal. The free run signal has negative or positive polarity depending on the HPOLO & VPOLO bit setting in the HV_CON control register, '1' is positive and '0' is negative polarity. After chip reset, ENV , ENH , FRFREQ & FRUN will enter HIGH state and P06 & P07 will act as I/O pins. Half frequency input and output: In this pin assignment, when ENHALF sets to '0' in SYNCON register, the HALFHO pin will act as an output pin and output half of input signal in the HALFHI pin with 50% duty (Refer to Figure 21). If NOHALF sets to '0', HALFHO will output the same signal in the HALFHI pin and user can control its polarity output of HALFHO by setting HALFPOL bit, '1' for positive and '0' for negative polarity. After chip reset, ENHALF , NOHALF & HALFPOL will be in the HIGH state and P13 & P17 will act as I/O pins.
29
NT68P61A
(1) HSYNCI Composite H sync. waveform (H EOR V) (2) HSYNCI Composite H sync. waveform (H OR V)
a
a
a
a
a
a
No matter Hsync pulse existing or not, the output signal of Hsync will be inserted.
2s
HSYNCO
a a a
Original Hsync Pulse
Inserted Hsync Pulse
Original Hsync Pulse
VSYNCO
Widen 9 s
Figure 18. Composite H & V Sync. Processing
30
NT68P61A
Sync. Mode Processing
System Default: S/C = '1' & HSEL = '1' Open INTV & clear INTV flag
Set S/C = '0' Clear VCNTOV & HCNTOV Open INTV & clear INTV flag Set S/C = '1' & HSEL = '0' Clear VCNTOV & HCNTOV Delay 10ms No
Freq. Calculating
INTV ? Yes Delay 31 ms Delay 60ms Yes HCNTH = '00' ? No Yes VCNTOV = '1' ? Yes VCNTOV = '1' ? Suspend Mode Off Mode
1. Extract VCNTL/H 12 bit data 2. HSEL = '1' 12 bit data X 8s = Vsync. time duration 3. Its reciprocal is Vsync. freq. 4. HSEL = '0' 12 bit data X 8.192ms = Vsync. freq.
No STAND-BY Mode Yes HCNTH = '00' ? NORMAL Mode Seperate Sync. No HCNTH ='00' ? No Yes Worng Mode No 1. Extract HCNTL/H 12 bit data 2. 12 bit data * Vsync. freq. = Hsync. freq. 3. Its reciprocal is Hsync. time duration.
Read VCNT|HCNT Counter Register
Read VCNT|HCNT Counter Register Return Freq. Calculating NORMAL Mode Composite Sync.
Return
Figure 19. H & V Sync. Software Control Flowchart (for reference only)
31
NT68P61A
61Hz
(1) 62.5KHz (2) 41.7KHz
(a) Free run output Vsync. signal
Pulse width 64 s
Pulse width 1 s (b) Option 2 of free run output Hsync. signal
Figure 20. Free Running Sync. Waveform
HALFHI
HALFHO: Half freq. output signal (50% duty)
HALFHO output signal when NOHALF bit clears to LOW (the same signal as in the HALFHI pin)
Figure 21. Half Freq. Sync. Waveform
32
NT68P61A
13.3. Power Saving Mode Detect: The VIDEO mode is listed below. Power saving is from mode 2 to mode 4. All modes can be detected by setting the control register properly. Refer to Figure 15 control flow chart for software reference. Mode (1) Normal (2) Stand by (3) Suspend (4) Off Control bit description:
Addr. $0005 $0006 $0007 $0008 $0009 $000A $000B $0011 Register MD CON HV CON HCNT L HCNT H VCNT L VCNT H SYNCON CLR FLG INIT 07H 2FH 00H 00H 00H 00H FFH 00H Bit7 HCNTOV HCL7 VCL7 NOHALF CLRHOV Bit6 VCNTOV HCL6 VCL6 ENHALF CLRVOV Bit5 HSYNCI HCL5 VCL5 CLRINTS Bit4 VSYNCI HCL4 VCL4 Bit3 INSEN HPOLI HCL3 HCH3 VCL3 VCH3 FRFREQ CLRINTA Bit2
-
H-Sync Active Inactive Active Inactive
V-Sync Active Active Inactive Inactive
Bit1 S/ C S/ C HPOLO HCL1 HCH1 VCL1 VCH1 ENH CLRINTE
Bit0 MD1/ 2 MD1/ 2 VPOLO HCL0 HCH0 VCL0 VCH0 ENV CLRINTV R W R W R R R R W W
HSEL VPOLI HCL2 HCH2 VCL2 VCH2 HALFPOL CLRINTR
FRUN
CLRINTD
MDCON control register: S/ C : The SYNC MODE control. If the input of V & H Sync are separate signals, set this bit to '1' (system default). If the input is composite signal, clear this bit. Under the COMPOSITE mode, NT68P61A will extract the V Sync form H Sync signal. HSEL : When clearing this bit, system will reset HCNTL|H counter to zero. The number of Hsync pulse at the 8.192ms interval is obtained. INSEN : User can clear this bit for inserting Hsync pulse when processing the composite signal. System will disable this function after reset. HVCON control register: HCNTOV: The overflow bit of H Sync. After setting bit '1' without any input Vsync pulses and HSEL there are more than 4096 Hsync pulses coming ,this bit will be set. It will keep '1' and user can clears it by setting CLRHOV bit to '1' at the CLRFLG control register. After cleared, the H Sync counter will reset to '0' and start counting for every Hsync pulse. VCNTOV: The overflow bit of V Sync. The operation is the same as HCNTOV. After cleared, the Vsync counter will reset to '0' and start counting for every 8s.
HSYNCI & VSYNCI:User can instantaneously detect input of H & V Sync pulse at any time. HPOLI & VPOLI: The polarity of input H & V Sync pulse - '1' for positive polarity and '0' for negative polarity. HPOLO & VPOLO:To control the output polarity of H & V Sync pulse - '1' for positive polarity and '0' for negative polarity. HCNTL|H & VCNTL|H control registers: The 12 bits counter for H & V Sync pulse. SYNCON control register:
ENH & ENV : Enable the output of H & V Sync. The P06 & P07 will switch to VSYNCO & HSYNCO output. FRUN : Open free run signal at the VSYNCO & HSYNCO output. FRFREQ : Select the free run frequency of H Sync output. ENHALF : P12 & P13 will switch to HALFHO & HALFHI pin. The HALFHO will output the half signal at the HALFHI pin with 50% duty. NOHALF : User must clear ENHALF first. The HALFHO will output the same signal at the HALFHI pin. HALFPOL: User must clear ENHALF first and control the
33
NT68P61A
polarity at the HALFHO output pin - '1' for positive polarity and '0' for negative polarity.
14. BASE TIMER (BT) The Base Timer is an 8-bit counter whose clock source must be chosen with 1s or 1ms by setting or clearing the TBS bit ('0' for 1s and '1' for 1ms). The BT can be enabled/disabled by the ENBT bit in the BTCON register. When user clearing this control bit to '0', the BT will start counting, otherwise setting this bit to '1' will stop the counting. After chip is reset, the TBS and ENBT bits are set to '1' (the BT is disabled). BT, can be preset by writing BT7 - BT0 to the BT register (write only) at any time and the BT will start count-up from preset value. When the value reaches FFH, it generates a timer interrupt if the timer interrupt is enabled. When it reaches the maximum value of FFH, the base timer will wrap around and begin counting at 00H. The timer interval can be within 256 ms maximum if set TBS to '1'. The timer interval can be within 256s maximum if set TBS to '0'.
1 s 1ms
0
BT7
BT6
BT5
BT4
BT3
BT2
BT1
BT0
1
TMR INT
TBS
Control bit description: Addr. $0016 $0017 Register BT BT CON INIT 00H 03H Bit7 BT7 Bit6 BT6 Bit5 BT5 Bit4 BT4 Bit3 BT3 Bit2 BT2 Bit1 BT1 TBS Bit0 BT0
ENBT
W W
BT control register : BT0 - BT7: Preloaded value of the base timer. The timer will count-up from this value. BTCON control register:
ENBT : When clearing this bit, the base timer will be activated. TBS: Select the input clock source of base timer - '1' for 1ms and '0' for 1s.
34
NT68P61A
15. I2C Bus Interface: DDC1 & DDC2B Slave Mode
I C bus interface is a two-wire, bi-directional serial bus which provides a simple, efficient way for data communication between devices. Its structure minimizes the cost of connecting various peripheral devices. In short, the wired-AND 2 2 connection of all I C interface to I C bus is the most important structure. Two modes of operation have been implemented in NT68P61A: UNI-DIRECTIONAL mode (DDC1 mode) and BI-DIRECTIONAL mode (DDC2B mode). If the MD1/ 2 bit is set to '1', the device will operate in the DDC1 mode, and if the MD 1/ 2 bit is cleared to '0', the device will operate in the 2 2 DDC2B mode. All of these I C functions will be activated only when ENDDC bit clears to '0' (in IISTS register). When I C bus function is activated, the P30 & P31 will switch to SCL & SDA pin. System works on the DDC1 mode transmission default. The SCL pin will remain high and SDA will transfer one bit of data at every rising edge of Vsync pulse.
2
SDA
Shift Register (IIDAT)
0 clock source 1
SCL VSYNC
MD1/2
15.1. DDC1 Bus Interface Vsync input and SDA pin: In DDC1 data transfer, the Vsync input pin is used as an input clock for data transmission and SDA output pin, as serial data line. This function comprises of two data buffers: one is a preloaded data buffer for user placing one bit of data in advance, and one is shift register for system shifting out one bit of data to the SDA pin. These two data buffer cooperate properly. Refer to Figure 18. After system 2 reset, the I C bus interface is in DDC1 mode. Data transfer: In advance, put one byte transmitted data 2 into IIDAT register and activate I C bus by setting ENDDC bit to '0' and open INTD interrupt source by setting IEINTD to '1'. On the first 9 rising edge of Vsync, system will shift out any invalid bit in shift register to SDA pin to empty shift register. When shift register is empty and on next rising edge of Vsync, it will load data in the IIDAT register to internal shift register. At the same time, NT68P61A will shift out MSB bit and generate an INTD interrupt to remind user to replace next byte data into IIDAT register. After eight rising clocks, there are eight bits shifted out in proper order and the shift register becomes empty again. At the ninth rising clock, it will shift the ninth bit (null bit '1') out to SDA. And on the next rising edge of Vsync clock, system will generate a INTD interrupt again. NT68P61A will also load new data in the IIDAT register to internal shift register and shift out one bit immediately. User must input new data to IIDAT register properly before the shift register is empty (the next INTD interrupt). Vsync clock: In the separate sync signal, the Vsync pulse is used as a data transfer clock. Its frequency allows 25KHz maximum. If no Vsync input signal is found, NT68P61A can not transmit any data to SDA pin regardless what the Vsync has extracted from composite Hsync signal.
35
NT68P61A
Control bit description:
Addr. $0005 Register MD CON INIT 07H Bit7 CLRHOV SR7 Bit6 CLRVOV SR6 Bit5 IEINTS IRQINTS CLRINTS SR5 START START Bit4 IEINTD IRQINTD CLRINTD SR4 STOP STOP Bit3 INSEN IEINTA IRQINTA CLRINTA SR3 ENDDC Bit2
-
Bit1 S/ C S/ C IEINTE IRQINTE CLRINTE SR1 RXAK
Bit0 MD1/ 2 MD1/ 2 IEINTV IRQINTV CLRINTV SR0 TXAK R W W R W RW R W
HSEL IEINTR IRQINTR CLRINTR SR2 TRX
$000F $0010 $0011 $0014 $0015
IEX IRQX CLR FLG II DAT II STS
00H 00H 00H 00H 08H
MDCON control register: MD1/ 2 : Select the DDC mode - '1' for DDC1 and '0' for DDC2B mode. System will be DDC1 mode by default. When transmission mode is changed form DDC1 to DDC2B, system automatically clears this bit. IEX control register: At DDC1 mode, only open INTD interrupt, as well as open INTS interrupt to detect if has changed to DDC2B mode. II_DAT control register: Data buffer for transmission. II_STS control register: ENDDC : When clearing this bit, system will activate DDC transmission. P30 & P31 will switch to SDA & SCL pin.
ENDDC (in IISTS register)
Vsync Pulse 1 2 3 4
a
a
a
a
a
a
9
1
2
3
4
5
6
7
8
9
1
2
INTV
a
a
a
a
a
a
Load data in the IIDAT register to shift register
a a a
INTD
a
a
a
User can load next byte data to IIDAT register
SDA
Invalid data
a
a
a
8
7
6
5
a
a
a
1
Null Bit
8
7
6
5
4
3
2
1
Null Bit
8
7
a
a
a
Shift register
Second Byte Data 8 MSB 7 6 5 4 3 2 1 LSB
First Byte Data
Figure 22. DDC1 Mode Timing Diagram
36
NT68P61A
15.2 DDC2B Slave Mode Bus Interface The DDC2B I C Bus Interface features are as follows: - SLAVE mode (NT68P61A addressed by a master which drive SCL signal) 2 - Fully compatible with I C bus standard - Interrupt and generation of acknowledge handled by user for communication - Interrupt driven byte by byte data transfer - Calling address identification interrupt - Detection of START and STOP signals Enable I C and INTS: The NT68P61A included the use in applications requiring storage and serial transmission of configuration and control information. User can place address data into IIADR register and set IEINTS to '1' (in IEX register) in advance. In the DDC1 mode (after clearing ENDDC to '0') and when the low level on the SCL pin occurs, NT68P61A will remind user by
2 2
generating a INTS interrupt and switch to DDC2B mode automatically. When user sets MD1/ 2 to '1' at this time, the NT68P61A will still proceed with a DDC1 communication. The DDC2B bus consists of two wires, SCL and SDA; SCL is for the data transmission clock and SDA is for the data line. Data transfers follow the format shown in Figure 19. The standard communication 2 of I C bus protocol includes four parts: a START signal, slave ADDRESS, transferred data (proceed byte by byte) and a STOP signal. In the wired-AND connection, any slow devices can hold the SCL line LOW to force the fast device into a wait state until the slow device is ready for the next bit or byte transfer in a type of handshake procedure.
START CONDITION
STOP CONDITION
SDA
aaa
aaa
aaa
SCL
1-7
8
9
1-7
8
9
1-7
8
9
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
IIDAT Reg. bit stream
8 MSB
7
6
5
4
aaa
1 LSB
ACK
8 MSB
7
6
5
4
3
2
1 LSB
ACK
8 MSB
7
a
a
a
Figure 23. DDC2B Data Transfer
37
NT68P61A
Start condition: When SCL & SDA lines are in HIGH state, an external device (master) may initiate communication by sending a START signal (defined as SDA from high to low transition while SCL is in high state). When there is a START condition, NT68P61A will set the 'START' bit to '1' and user can poll this status bit to control DDC2B transmission at any time. This bit will keep '1' until user clears it. After sending a START signal for DDC2B communication, an external device can repeatedly send start conditions without sending a STOP signal to terminate this communication. This is used by the external device to communicate with another slave or with the same slave in different mode (READ or WRITE mode) without releasing the bus. Address matched and INTA: After the START condition, 2 a slave address is sent by external device. When I C bus interface changes to DDC2B mode, NT68P61A will first act as a receiver to receive this one byte data. This address data is 7 bits long followed by the eighth bit that indicates the data transfer direction (R/ W ). When NT68P61A system receives address data from external device, it will store if in IIDAT register. System support 'A0' address by default and another one set of DDC2 address for user. When user enable DDC2 function, the system will compare address data getting from external device with the default address 'A0' and data in the $0013 II_ADR control register written by user. Either of these address matched, the system will generate an INTA interrupt flag and this DDC2 communication will be continued. If user sets IEINTA bit to '1' in advanced and address data matched, the NT68P61A system will generate a INTA interrupt. Under the address matching condition, the NT68P61A will send an acknowledgment to external device. If address data not matched, the NT68P61A will not generate INTA interrupt and not care the data change on SDA line in the future. Data Transmission direction: At INTA interrupt servicing routine, user must check the LSB of address data in 2 IIDAT register. According to I C bus protocol, this bit indicates the DDC2B data transfer direction in later transmission - a '1' indicates a request for 'READ MODE' action (external read data from system); a '0' indicates a 'WRITE MODE' action (external write data to system). For READ mode and WRITE mode timing diagram refer to Figure 24 and 25. The data transfer can be proceeded byte by byte in a direction specified by the R/ W bit after a successful slave address is received. User must set TRX bit in the IISTS register for NT68P61A transmission mode - '1' for READ mode and '0' for WRITE mode. Data validity and transfer: The data on the SDA line mu be stable during the HIGH period of the clock on the SCL line. The HIGH and LOW state of the SDA line can only change when the clock signal on the SCL line is LOW. Each byte data is eight bits long and one clock pulse for one bit of data transfer. Data is transferred with the most significant bit (MSB) first. If a receiver (external device or NT68P61A) cannot receive another complete byte of data until it has performed some other function, for example servicing an internal interrupt, it can hold the clock line SCL LOW to force the transmitter into a wait state. Data transfer then continues when the receiver is ready for another byte of data and release clock line SCL. Each byte data is followed by an acknowledge bit. Acknowledge: The acknowledgment will be generated at ninth clock by whom receive data. In the WRITE mode, NT68P61A system must respond to this acknowledgment. After receiving one byte data from external device, NT68P61A will automatically send an acknowledgment by pulling SDA line to 'LOW'. In the READ MODE, external device must respond to this acknowledgment and at every byte data sent, user can read RXAK bit in IISTS register to check if external sent a ACK or not. The INTD interrupt: After NT68P61A receive the START condition, it will generate an INTD interrupt at the falling edge of the ninth clock. User can control the flow of DDC2B transmission at this INTD interrupt. The INTD on the WRITE mode: NT68P61A read data from external device. At INTD interrupt, the SCL will be hold LOW by NT68P61A. When getting one byte data from II_DAT register, user can write '00' into II_DAT register and the SCL will be released. External device can continue sending next byte data to NT68P61A. Refer to Figure 24. The INTD on the READ mode: External device read data from NT68P61A. At INTD interrupt, the SCL will be hold LOW by NT68P61A. User can check RXACK bit in the IISTS register whether external device has sent an ACK or not after one byte data transfer. If external device has sent an ACK, the RXACK will be '0' (assume the acknowledgment is LOW signal). When user puts one new byte data into II_DAT register, the SCL will be released for generation of SCL transmission clock. The next byte data will be shifted out properly. Refer to Figure 25.
38
NT68P61A
STOP condition: When SCL & SDA lines have been released (remain in 'HIGH' state), DDC2B data transfer is always terminated by a STOP condition generated by external device. A STOP signal is defined as a low to high transition of SDA while SCL is in HIGH state. When there is a STOP condition, NT68P61A will set the 'STOP' bit to '1' and user can poll this status bit to control DDC2B transmission at any time. This bit keeps '1' until user clears it. Notice the SCL and SDA lines must 2 conform to I C bus specifications. (Refer to Figure 26). 2 Refer to the standard I C bus specification for details. Control bit description:
Addr. $0005 Register MD CON INIT 07H Bit7 CLRHOV AR7 SR7 Bit6 CLRVOV AR6 SR6 Bit5 IEINTS IRQINTS CLRINTS AR5 SR5 START START Bit4 IEINTD IRQINTD CLRINTD AR4 SR4 STOP STOP Bit3 INSEN IEINTA IRQINTA CLRINTA AR3 SR3 Bit2
-
Changing to DDC1 mode: After an external device terminates DDC2 transmission, set MDI/ 2 to 1 for changing to DCC1 mode. When the SCL line has been released (pulled-up), user can force NT68P61A to DDC1 mode communication at any time. This function is supporting the 'error' recovery protocol in the VESA DDC standard Ver 2.0.
Bit1 S/ C S/ C IEINTE IRQINTE CLRINTE AR1 SR1 RXAK
Bit0 MD1/ 2 MD1/ 2 IEINTV IRQINTV CLRINTV SR0 R W W R W W RW R W
HSEL IEINTR IRQINTR CLRINTR AR2 SR2 TRX
$000F $0010 $0011 $0013 $0014 $0015
IEX IRQX CLR FLG II ADR II DAT II STS
00H 00H 00H FFH 00H 08H
ENDDC
MDCON control register: MD1/ 2 : Select the DDC mode - '1' for DDC1 and '0' for DDC2B mode. System will be DDC1 mode by default. When transmission mode is changed form DDC1 to DDC2B, system will automatically clear this bit. IEX control register: In DDC2 mode, user use INTS, INTA & INTD interrupt and II_STS control register to control DDC2B transmission. II_DAT control register: Data buffer for transmission
II_ADR control register: User can define the address of DDC2B device. If an external device sends the same address data as this control register (calling NT68P61A), NT68P61A will generate an INTA interrupt. II_STS control register:
ENDDC : When clearing this bit, the system will activate DDC transmission. P30 and P31 will switch to SDA and SCL pin. TRX: In the READ mode of DDC2B transmission, user must set this bit '1'. RXAK: In the WRITE mode of DDC2B transmission, after one byte has been sent out to the SDA line, there will be an INTD interrupt. At INTD interrupt service routine, user can check this bit to see if external device has responded to NT68P61A.
39
NT68P61A
S
NT68P61A Address
R/W
A
DATA
A
DATA
A
P
0 From external device to NT68P61A From NT68P61A to external device
Data transferred from external device A = acknowledge S = START P = STOP
(a) WRITE_Mode Data Format
wait wait wait
wait SCL
START SDA (external device) 1 0 1 0 0 0 0
R/W 0 DATA DATA
STOP
INTS
INTA
INTD SDA (NT68P61A)
A
A
A
(b) WRITE_Mode Timing Diagram
Figure 24. DDC2B Write_Mode Spec.
40
NT68P61A
S
NT68P61A Address
R/W
A
DATA
A
DATA
A
P
1 From external device to NT68P61A
Data transferred from external device A = acknowledge A = no acknowledge
From NT68P61A to external device
O 3/4 OOAOO N 3/4 OON
(a) Read_Mode Data Format
wait SCL wait wait wait
START SDA (external device) 1 0 1 0 0 0 0
R/W 1
STOP
A
A
INTS
INTA
INTD SDA (NT68P61A)
A
DATA
DATA
(b) READ_Mode Timing Diagram
Figure 25. DDC2B Read_Mode Spec.
41
NT68P61A
Interrupt Service Routine
Polling Need Polling INTS ? yes Open INTV & INTS INTS ? No No INTD ? INTA ? No INTV ? No INTR ? No No Need Polling INTD ? yes No Need Polling INTA ? yes No Need Polling INTV ? yes No Need Polling INTR ? yes No
Main Program
Set ENDDC = 0
DDC2
yes
yes
yes Reset EDID Buffer Index From IIDAT Reg. LSB To Decide Write/Read Mode DDC2B Read_Mode Operation
DDC1
yes
yes
Change To DDC2 Mode MD 1/2 = 0 (Auto Switch) Wait Interrupt or Doing something
DDC1 Transfer ? yes
No
DDC2B Write_Mode Operation ? yes
No
Change To DDC1 Mode MD_CON = 1
Put Addr. Into IIADR Reg.
From EDID Buffer Index Put One Byte Data Into IIDAT Reg.
Read One Byte Data From IIDAT Reg. To Set EDID Buffer Index
Setting IISTS: TRX = 0 (Recv. Mode)
Write '00' To IIDAT For releasing SCL
From EDID Buffer Index Put One Byte Data Into IIDAT Reg.
DDC2B Write_Mode Operation ? yes
No
Reset EDID Buffer Index Put One Byte Data Into IIDAT Reg.
Other INT. Service
Setting IISTS: TRX = 0 (Recv. Mode)
Setting IISTS: TRX = 1 (Trans. Mode)
Open INTS & INTD
NO No Open INTA & INTR Open INTS & INTD DDC2 Operate Over ? yes Reset EDID Buffer Index Put First Byte Data Into IIDAT Reg. For releaseing SCL & For Transfer data
DDC2 Idle For 2 Sec. ?
Write '00' To IIDAT For releasing SCL
yes Return To DDC1 Mode Open INTV
Open INTA & INTD Open INTA & INTD
Open INTA & INTV
Return
Figure 26. DDC1/2B Software Flow Chart
42
NT68P61A
Absolute Maximum Ratings*
DC Supply Voltage VDD - VSS . . . . . . . . . . . .-0.3V to 7V Input Voltage . . . . . . . . . . . . . . GND -0.2V to VCC +0.2V Operating Temperature . . . . . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . -50C to +125C
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposed to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics (VDD = 5V, TA = 25C, oscillator freq. = 8MHz, unless otherwise specified)
Symbol IDD VIH1 VIH2 VIL1 VIL2 IIH VOH1 Parameter Operating Current Input High Voltage Input High Voltage Input Low Voltage Input Low Voltage Input High Current Output High Voltage 2.4 -200 2 3 0.8 1.5 -350 Min . Typ. Max . 20 Unit mA V V V V A V No loading P00 - P07, P10-P16, P20-P27, P30, P31, RESET , VSYNCI, HSYNCI, HALFHI, INTE SCL, SDA pins P00 - P07, P10 - P16, P20 - P27, P30, P31, RESET , VSYNCI, HSYNCI, HALFHI, INTE SCL, SDA pins P00 - P07, P10 - P16 ,P20 -P27, VSYNCI, HSYNCI, HALFHI, RESET (VIH = 2.4V) P00 - P07, P10 - P15 (IOH = -100A) VSYNCO, HSYNCO (IOH = -4mA) HALFHO (IOH = -4mA) P20-P27 (IOH = -10mA) external applied voltage external applied voltage P00 - P07, P10 - P15, DAC0 - 13 (IOL = 4mA) SCL/P30, SDA/P31 (IOL = 5mA) VSYNCO, HSYNCO (IOL = 4mA) HALFHO (IOL = 4mA) P20 - P27 (IOL = 10mA) Conditions
VOH2 VOH3 VOL
Output High Voltage (DAC8 DAC13) Output High Voltage (DAC0 - DAC7) Output Low Voltage
5 12 0.4
V V V
VLVR ROL ROH1 ROH2 ROH3
Low Voltage Threshold Pull Down Resistor ( RESET ) Pull Up Resistor (INTE) Pull Up Resistor (PORT0 & PORT1) Pull Up Resistor (HSYNCI & VSYNCI) 25K 11K 11K 11K
4.0 50K 22K 22K 22K 75K 33K 33K 33K
V
43
NT68P61A
AC Electrical Characteristics(VDD = 5V, TA = 25C, oscillator freq. = 8MHz, unless otherwise specified)
Symbol Fsys tCNVT Voffset Vlinear tinst tdev System Clock A/D Conversion Time A/D Converter Offset Error A/D Input Dynamic Range of Linearity Conversion The Inserted Hsync Pulse Width The time deviation at the end edge of inserted Hsync pulse Reset Pulse Width Low Vsync Input Frequency Vsync Input Pulse Width Hsync Input Frequency Hsync Input Pulse Width High Hsync Input Pulse Width Low Counting Deviation of Base Timer Counting Deviation of Base Timer 2 32 8 30 0.5 8 1 1 25K 300 120 7 0.3 2 250 Parameter Min. Typ. 8 375 39 0.7 Max. Unit MHz s mV VDD s ns Composite sync (Refer Figure 18) Composite mode & insertion function activated tCYCLE = 2/Fsys tVSYNC = 1/Fvsync Vin = 2V for A/D converter Condition
tRESET Fvsync tVPW Fhsync tHPW1 tHPW2 tERROR1 tERROR2
tCYCLE Hz s KHz s s s ms
tHSYNC = 1/Fhsync
Composite sync 1s clock source 1ms clock source
44
NT68P61A
DDC1 Mode
Symbol tVPW Fvsync tDD tMODE Parameter Vsync High Time Vsync Input Frequency Data Valid Time for Transition to DDC2B Mode Min. 0.5 32 200 Typ. Max. 300 25K 500 500 Unit us Hz ns ns tVSYNC = 1/Fvsync Condition
SCL
tMODE tDD
SDA
Bit 0
Null Bit
Bit 7
Bit 6
VSYNC
tVPW
Composite Hsync Input
aaa
tHPW2 tHPW1
Extracted Vsync Output (no loading)
45
NT68P61A
DDC2B Mode Symbol fSCL tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO Parameter SCL Clock Frequency Bus Free Between a STOP and START Condition Hold Time for START Condition LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Set-up Time for STOP Condition 4 4.7 4 4.7 4 4.7 300 300 1 300 Min. Typ. Max. 100 Unit KHz s s s s s ns ns s ns s
SDA
tBUF
tLOW
tR
tF
tHD; ST A
SCL
tHD; STA STOP START
tHD; DAT tHIGH
tSU; DAT START
tSU; S T A
tSU; ST O STOP
46
NT68P61A
Ordering Information
Part No. NT68P61A Package 40L DIP
47
NT68P61A
Package Information DIP 40L Outline Dimensions
D 40 21
unit: inches/mm
E1
1 S
20 E C
A2
A
A1
Base Plane
Seating Plane B B1 e1 eA
L
Symbol A A1 A2 B
Dimensions in inches 0.210 Max. 0.010 Min. 0.1550.010 0.018 +0.004 -0.002 0.050 +0.004 -0.002 0.010 +0.004 -0.002 2.055 Typ. (2.075 Max.) 0.6000.010 0.550 Typ. (0.562 Max.) 0.1000.010 0.1300.010 0 ~ 15 0.6550.035 0.093 Max.
Dimensions in mm 5.33 Max. 0.25 Min. 3.940.25 0.46 +0.10 -0.05 1.27 +0.10 -0.05 0.25 +0.10 -0.05 52.20 Typ. (52.71 Max.) 15.240.25 13.97 Typ. (14.27 Max.) 2.540.25 3.300.25 0 ~ 15 16.640.89 2.36 Max.
B1
C D E E1 e1 L eA S
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E1 does not include resin fins. 3. Dimension S includes end flash.
48

▲Up To Search▲

Price & Availability of NT68P61A

	To Download NT68P61A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .